The present invention relates to a semiconductor memory device, and more particularly to an internal signal detector for detecting any defects from each internal circuit in the semiconductor memory device.
Recently, there has been an increased demand for semiconductor memory devices that are capable of having high integration and high storage capacity. As semiconductor memory devices are increasingly integrated to obtain greater storage capacity, the number of defects among the memory circuits concomitantly increases to contribute to a low yield in the productivity of these semiconductor memory devices. In order to address problems of defects and low yield, the defect memory circuit of the semiconductor memory devices must be detected.
However, it is very difficult to detect the defective circuit or element thereof in a highly integrated semiconductor memory device over 1 mega byte or 4 mega byte. Moreover, even if the defects are detected, their detecting time is too long.
FIG. 1 shows an internal signal (or circuit) detector of a prior art. The circuit of FIG. 1 detects the defects of an internal signal by using a probing method. The probing method is used to detect the defects and to check the potential characteristic by erecting a probe on a transistor or a pad of the integrated circuit. First and second signal generators 3 and 4 in the chip generate the signals indicating the operational characteristic of circuits or elements thereof in a chip. Although the circuit of FIG. 1 comprises two signal generators, a plurality of signal generators can be included also. First and second probes 1 and 2 are located on the surface of chip, to detect the internal signal signifying the defective element of the chip. In the following, the detecting operation of the internal signal signifying the defective elements of the chip will be described. The first and second transmission probes 1 and 2 are erected on lines connecting the first signal generator 3 and the second signal generator 4; the transmission lines receive signals S.sub.1 and S.sub.2 generated by the first and second signal generators 3 and 4. Thereafter, whether the signals S.sub.1 and S.sub.2 detected between the first and second signal generators 3 and 4 are normal or not is checked by operation of the first and second probes and 2. However, this process, i.e., to obtain the potential value of each node through the physical or electrical probing operation, takes a considerably long debugging time in order to detect the defects. Further, since the higher density is provided to the integrated circuit, the internal circuit becomes more complicated. Accordingly the debugging time increases substantially.